Model Technology Model Sim EE manuals

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Table of contents

ModelSim EE/SE

1

Command Reference

1

Software License Agreement

3

Important Notice

4

Limited Warranty

5

Table of Contents

6

Table of Contents - 7

7

Command Syntax and Conven

8

Index (CR-257)

8

ModelSim Commands

9

Command reference table

10

[<n>

19

<n>

19

(CR-139)

19

(CR-93)

25

-file <filename>

46

-time <limit>

46

(CR-51)

52

<filename> [ -keep ]

60

<name>

63

(CR-77)

64

(CR-134)

64

(CR-235)

69

<item_name>

73

(CR-64)

77

[-force]

84

(CR-248)

86

<args>

92

.main clear

99

CR-101

101

CR-103

103

<filename> [-r

104

<filename>

104

-r

104

CR-105

105

CR-107

107

CR-109

109

CR-111

111

CR-113

113

CR-115

115

CR-117

117

(CR-120)

118

CR-119

119

CR-121

121

CR-123

123

CR-125

125

CR-127

127

CR-129

129

[<filename>]

130

CR-131

131

CR-133

133

CR-135

135

CR-137

137

(CR-146)

138

CR-139

139

(CR-151)

140

CR-141

141

CR-143

143

CR-145

145

CR-147

147

CR-149

149

CR-151

151

CR-153

153

CR-155

155

CR-157

157

CR-159

159

CR-161

161

<comment string>

162

CR-163

163

CR-165

165

<filesize>

166

CR-167

167

CR-169

169

CR-171

171

CR-173

173

ARITHMETIC.”=”(left, right)

174

(2-41) for more information

174

CR-175

175

CR-177

177

CR-179

179

CR-181

181

CR-183

183

CR-185

185

CR-187

187

CR-189

189

CR-191

191

CR-193

193

CR-195

195

CR-197

197

CR-199

199

CR-201

201

CR-203

203

CR-205

205

CR-207

207

CR-209

209

CR-211

211

CR-213

213

CR-215

215

CR-217

217

CR-219

219

.wave.tree zoomfull

221

.wave.tree zoomrange

222

CR-223

223

-o <outfile>

224

<wavfile>

224

CR-225

225

CR-227

227

CR-229

229

CR-231

231

CR-233

233

CR-235

235

-window <wname>

236

(CR-180)

236

CR-237

237

CR-239

239

Chapter contents

241

Syntax conventions

242

Command return values

243

Numbering conventions

244

HDL item pathnames

245

Absolute path names

246

Relative pathnames

246

Name case sensitivity

246

Extended identifiers

247

Naming fields in VHDL signals

247

Wildcard characters

248

ModelSim variables

248

Simulation time units

249

GUI_expression_format

250

CR-251

251

VHDL record field support

252

Grouping and precedence

252

Saving expressions

253

Expression syntax

253

CR-255

255

/top/bus and $bit_mask

256

Model Technology

264

Table of contents

ModelSim EE/PLUS

1

Tutorial

1

Important Notice

4

Limited Warranty

5

Table of Contents

6

3 - ModelSim EE Lessons (p91)

8

Index (p167)

9

Introduction

11

’s graphic interface

12

Standards supported

12

Assumptions

13

Sections in this document

13

Text conventions

14

Syntax conventions

14

Comments

16

EE Graphic Interface

17

Window overview

18

Window features

19

Tree window hierarchical view

22

Main window

24

The Main window menu bar

25

The Main window tool bar

30

The Main window status bar

32

Dataflow window

35

The Dataflow window menu bar

36

List window

38

The List window menu bar

40

.list.tbl config -usegating 1

43

HDL items to the List window

44

Examinin

47

List window data to a file

51

Process window

52

The Process window menu bar

53

Signals window

55

Source window

61

The Source window menu bar

62

The Source window tool bar

64

Source window options

66

Structure window

67

The Structure window menu bar

68

Variables window

70

The Variables window menu bar

71

Wave window

73

Wave window action list

74

The Wave window menu bar

75

Wave window tool bar

78

EE Lessons

91

Commands and their history

92

Basic VHDL simulation

94

(PROMPT: vcom counter.vhd)

96

(PROMPT: vsim counter)

96

(PROMPT: add wave /counter/*)

98

(KEYBOARD: control+c)

100

(PROMPT: bp counter.vhd 18)

100

Debugging a VHDL design

103

(PROMPT: run)

105

add wave *

113

add list *

113

quit -f

113

Executing commands at startup

114

Tcl/Tk and Model

115

How Tcl/Tk works with Model

116

The custom-traffic-li

117

Tcl/Tk and ModelSim

118

Copies of the ori

119

Example shortcuts

121

Preparin

121

for the Tcl/Tk examples

121

Example 3 - The traffic li

124

Basic Verilog simulation

129

(PROMPT: vlib work)

130

(PROMPT: vlog counter.v)

131

(PROMPT: vsim test_counter)

132

view signals list wave

133

(PROMPT: add list /counter/*)

133

quit -force

142

Mixed VHDL/Verilog simulation

143

(PROMPT: vlib mixed)

144

(PROMPT: vmap work mixed)

144

(PROMPT: vsim top)

146

(PROMPT: view *)

146

Using the Wave window

153

.wave.tree zoomrange f1 f2

156

Continuing with Model

158

Updates

162

Licenses - Model

162

/usr/mti5.2/sunos5/options

164

Online References

165

Model Technology

171

Table of contents

Getting Started

1

ModelSim PE

1

Software License Agreement

3

Important Notice

5

Limited Warranty

5

Table of Contents

6

4 - Tutorial: Using Model

8

PE (p77)

8

B - Resources (p135)

9

Index (p143)

9

Introduction

11

Standards supported

12

Assumptions

13

Sections in this guide

13

Text conventions

14

Syntax conventions

14

Download a free PDF reader

15

Comments

16

ModelSim PE Installation

17

Current customers information

18

System requirements for Model

18

Installation procedure

19

To Run from the CD-ROM

20

ModelSim PE Graphic Interface

21

application window

22

ModelSim application window

23

menu bar

24

tool bar

27

Tree windows

29

Window overview

31

Transcript window

32

Dataflow window

35

Dataflow window mouse actions

36

List window

37

List window menu bar

38

List window status bar

39

List window mouse actions

39

Selecting HDL items to list

40

Formatting a list

41

Editing a list

43

Saving a listing

43

Updating the List window

44

Process window

45

Process window status bar

46

Process window mouse actions

46

Signals window

47

Signals window mouse actions

48

Forcing HDL item values

49

Source window

52

Source window status bar

53

Selecting the source file

53

Editing breakpoints

54

Customizing the Source window

54

Structure window

56

Structure window status bar

58

Variables window

59

Variables window status bar

60

Wave window

61

Wave window menu bar

62

Wave window status bar

63

Wave window mouse actions

63

Formatting the Wave window

65

Analog formatting

68

Literal formatting

68

Logic Formatting

69

Zooming the Wave window

69

Using the Wave window cursors

70

Writing a PostScript file

71

Customizing Model

72

windows

72

Changing window colors

73

Changing window fonts

73

Saving your window settings

74

Customizing ModelSim windows

75

Keyboard shortcuts

76

Tutorial: Using ModelSim PE

77

Tutorial setup

78

Basic VHDL simulation

79

Debugging a VHDL design

100

Basic Verilog simulation

105

Mixed VHDL/Verilog simulation

120

Step 11

124

Learning more about Model

127

’s windows

127

Continuing with Model

129

Help, Updates, and Licensing

131

Updates

132

PE Licensing

132

ModelSim PE Licensing

133

Getting help

134

Resources

135

Organizations

137

Online resources

141

Table of contents

ModelSim EE/PLUS

1

Reference Manual

1

Important Notice

4

Limited Warranty

5

Table of Contents

6

5 - Model

8

Command Reference (p67)

8

9 - The TextIO Package (p425)

16

15 - Using Tcl (p513)

19

Index (p555)

21

Introduction

23

’s graphic interface

24

Standards supported

24

Assumptions

25

Sections in this document

25

Simulation action list

27

Installed technotes

28

Text conventions

29

Comments

31

Design Libraries

33

Design library contents

34

Design library types

34

Library management commands

35

Working with design libraries

35

a library

41

VHDL resource libraries

41

Predefined libraries

42

Verilog resource libraries

44

Compilation and Simulation

45

VHDL &

46

The Verilo

52

‘uselib compiler directive

52

Mapping data types

58

instantiation criteria

62

Component declaration

62

VHDL instantiation criteria

65

SDF annotation

66

Command Reference

67

-do <macrofile>

69

-project <project file>

69

-nodebug[=ports]

73

-novital

73

-novitalcheck

73

-nowarn <number>

73

EE Graphic Interface

103

Graphic interface commands

105

Command-line simulation

107

Customizin

108

the interface

108

Window overview

109

Window features

110

Tree window hierarchical view

114

Main window

116

The Main window menu bar

117

The Main window tool bar

122

The Main window status bar

124

Dataflow window

127

The Dataflow window menu bar

128

List window

131

List window action list

132

The List window menu bar

133

.list.tbl config -usegating 1

136

HDL items to the List window

137

Examinin

141

List window data to a file

146

Process window

147

The Process window menu bar

148

Signals window

150

Source window

156

The Source window menu bar

157

The Source window tool bar

159

Source window options

161

Structure window

162

The Structure window menu bar

163

Variables window

165

The Variables window menu bar

166

Wave window

168

Wave window action list

169

The Wave window menu bar

170

Wave window tool bar

173

Searchin

181

VHDL compiler options pa

193

ARITHMETIC.”=”(left, right)

195

preferences from the Model

215

command line

215

Preference variable arrays

216

Menu preference variables

217

Window preference variables

217

Library desi

224

Force mappin

229

preferences

229

The Button Adder

230

The Macro Helper

231

The Tcl Debu

232

GUI_expression_format

236

(/memory/state == reading)

237

$<name>

237

/top/bus and $bit_mask

240

The GUI Expression Builder

242

Simulator Command Reference

245

Command return values

246

Syntax conventions

246

Command history shortcuts

247

Numbering conventions

247

HDL item pathnames

249

Wildcard characters

251

Tcl variables

252

Simulator control variables

253

Environment variables

255

Simulation time units

256

[<n>

257

<n>

257

-activebackground red}

259

<window_name>

269

<menu_path>

269

-flatten

274

<aka>

275

<cmds>

275

} else {

276

<filename>

277

<line_number>

277

<dir>

280

<variable>

281

<value>

281

-file <filename>

284

-time <limit>

284

<name>

298

<item_name>

306

<item_name>

306

[<filename>]

308

[-force]

316

<time>

320

[-window <wname>]

322

-window <wname>

322

<args>

324

-internal

326

-howmany

326

.main clear

330

command

331

<filename> [-r

335

-r

335

<command>

337

VSIM (pause)7>

340

<pattern>

347

[-force] [-sim]

351

-unsigned

352

-nocompress

357

[-over] [<n>]

371

-summary

376

<comment string>

381

-direction

383

-dumpports

383

<filesize>

385

<logical_name>

390

<path>

390

.wave.tree zoomfull

396

.wave.tree zoomrange

397

[[-label <label>]

398

-label <label>

398

and c /= 0 } {

400

echo “b is 1 and c is not 0”

400

.<win>.tree color

402

<preference file name>

405

Chapter contents

413

Choosing project files

414

Project file variables

415

[vcom] section

416

[Library] section

416

] section

418

[vsim] section

419

Variable functions

421

The TextIO Package

425

TextIO implementation issues

427

and VITAL

431

VITAL packages

432

VITAL compliance

432

Show_VitalChecksWarnings = 0

433

-O0

434

-debugVA

434

Standard Delay Format (SDF)

435

Timing Annotation

435

Instance specification

436

VHDL VITAL SDF

438

Resolvin

439

Verilog SDF

440

SDF to Verilo

442

construct matchin

442

Optional ed

445

Optional conditions

446

Rounded timin

446

Interconnect delays

447

Troubleshooting

448

PLI application requirements

452

HP700 linkin

454

IBM RISC/6000 linkin

454

Declarin

456

the FOREIGN attribute

456

The C initialization function

457

C code and VHDL examples

460

Support for Verilog instances

465

VSIM function descriptions

467

to VHDL data types

481

Enumerations

482

Reals and time

482

Using the Verilog PLI

483

Support for VHDL objects

484

FLI and PLI tracing

486

a trace

487

Installin

488

the dummy component

488

-trace_foreign 16

489

-trace_foreign 17

489

-trace_foreign 18

489

-trace_foreign 19

489

Value Change Dump (VCD) Files

491

VCD commands and VCD tasks

492

VHDL source code

494

VCD simulator commands

495

VCD output

495

Supported TSSI states

498

Port identifier code

499

Logic Modeling Library and

501

Hardware Modeler

501

VHDL SmartModel interface

502

SM_ENTITY

503

Entity details

505

Architecture details

505

Vector ports

505

Simulation

506

SPARCstation note

507

Command channel

507

SmartModel Windows for VHDL

508

Verilog SmartModel interface

510

Using Tcl

513

Tcl commands

514

Command substitution

515

Command separator

516

Multiple-line commands

516

Evaluation order

516

Variable substitution

517

System commands

517

List processing

518

VSIM Tcl commands

518

Tcl examples

519

Updates

524

Licenses - Model

524

/usr/mti5.2/sunos5/options

526

Online References

527

Tips and Techniques

529

How to use checkpoint/restore

530

Command-line mode

532

Batch mode

533

Passing parameters to macros

534

Saving and viewing waveforms

535

Bus contention checking

536

Bus float checking

537

Design stability checking

537

Toggle checking

538

location mappin

539

/home/vhdl/src

540

/usr/vhdl/src

540

/usr/modeltech/ieee

540

Modeling memory in VHDL

541

Appendix contents

547

Automatic start at boot time

549

Format of the license file

550

License administration tools

552

[-c <license_file>]

554

Model Technology

570

Table of contents

ModelSim

1

Software License Agreement

3

Rev. 10/99

8

Table of Contents

9

4 - VHDL Simulation (45)

10

5 - Verilog Simulation (55)

10

Table of Contents - 11

11

Table of Contents - 13

13

10 - Tcl and ModelSim (241)

15

A - ModelSim Variables (255)

15

B - ModelSim Shortcuts (287)

16

C - Tips and Techniques (291)

16

Index (301)

16

1 - Introduction

17

Standards supported

18

Assumptions

18

Sections in this document

19

Command reference

20

Text conventions

20

2 - Design Libraries

23

Design library contents

24

Design library types

24

Library management commands

25

Working with design libraries

25

(2-25) dialog box

30

(CR-111):

30

Moving a library

31

VHDL resource libraries

32

Predefined libraries

32

(CR-141) with the -refresh

33

What is a project?

36

A new file extension

36

INI and MPF file comparison

36

Project operations

37

Creating a Project

38

Working with a Project

41

The project command

42

4 - VHDL Simulation

43

Compiling VHDL designs

44

Simulating VHDL designs

45

Using the TextIO package

47

TextIO implementation issues

48

Dangling pointers

49

The ENDLINE function

50

The ENDFILE function

50

Providing stimulus

50

VITAL packages

51

ModelSim VITAL compliance

51

VITAL compliance checking

52

5 - Verilog Simulation

53

ModelSim variables

54

Compilation

55

Incremental compilation

56

Library usage

58

+libext+<suffix>

62

+librescan

62

+nolibcell

62

-R <simargs>

62

Simulation

65

Event order issues

66

Cell Libraries

71

System Tasks

72

[delayed_data])

76

Compiler Directives

78

Using the Verilog PLI

80

The callback reason argument

85

The sizetf callback function

86

Object handles

87

Third party PLI applications

87

Support for VHDL objects

88

IEEE Std 1364 ACC routines

89

IEEE Std 1364 TF routines

91

PLI tracing

93

<action>

94

-tag <name>

94

Opening and viewing datasets

96

(CR-23)

97

Virtual signals

101

Virtual functions

102

Virtual regions

102

Virtual types

103

ModelSim XE Graphic Interface

105

Window overview

106

Window features

107

Quick access toolbars

108

Drag and Drop

108

Command history

109

Automatic window updating

109

Sorting HDL items

110

Menu tear off

110

Tree window hierarchical view

111

(7-139)

112

(7-150), and

112

(7-183)

112

Main window

113

The Main window menu bar

114

(7-116) in the

118

The Main window tool bar

119

The Main window status bar

121

Dataflow window

124

The Dataflow window menu bar

125

(7-144) and the Process

126

List window

128

The List window menu bar

129

(CR-116)

130

(7-131)

137

Process window

142

The Process window menu bar

143

Signals window

144

(7-111) for more information

145

The Signals window menu bar

146

Forcing signal and net values

147

(CR-56)

148

(CR-67)

148

Defining clock signals

151

Source window

152

The Source window menu bar

153

(CR-51)

154

The Source window tool bar

155

(CR-93) command

156

Setting Source window options

157

Structure window

158

The Structure window menu bar

159

Variables window

161

The Variables window menu bar

162

Wave window

164

Wave window panes

167

HDL items you can view

168

The Wave window menu bar

169

Wave window tool bar

172

(CR-86)

174

(7-113)

176

(7-182).)

178

(7-170) menu

179

(CR-81). Item values

180

Sorting a group of HDL items

183

Saving waveforms

189

(CR-106). Edit the

197

(A-261) in the

199

Design selection page

203

VHDL settings page

205

Verilog settings page

207

(CR-140)

208

SDF settings page

209

(8-218)

210

(CR-70) to edit the

211

(3-35) for more

211

ModelSim Quick Start

214

Chapter contents

217

SDF and ModelSim XE

218

Instance specification

218

Errors and warnings

219

VHDL VITAL SDF

220

Resolving errors

221

Verilog SDF

222

Optional edge specifications

227

Optional conditions

228

Interconnect delays

229

Troubleshooting

230

Value Change Dump (VCD) Files

233

VHDL source code

234

VCD simulator commands

235

VCD output

235

10 - Tcl and ModelSim

239

Tcl features within ModelSim

240

Tcl References

240

Tcl commands

241

Tcl command syntax

242

$name(index)

243

10-245

245

Command substitution

246

Command separator

247

Multiple-line commands

247

Evaluation order

247

Variable substitution

248

List processing

249

VSIM Tcl commands

250

ModelSim Tcl time commands

250

Conversions

251

Relations

251

Arithmetic

252

A - ModelSim Variables

253

Variable settings report

254

Personal preferences

254

Environment variables

255

Removing temp files (VSOUT)

258

(CR-148)

264

(CR-86); NOTE - the

265

Variable functions

267

DelayFileOpen = 1

270

User-defined variables

271

Preference variable arrays

272

The addons variable

275

More preferences

281

(A-256) environment variable

282

Simulator state variables

283

B - ModelSim Shortcuts

285

Command shortcuts

286

Command history shortcuts

287

Right mouse button

288

C - Tips and Techniques

289

Passing parameters to macros

291

Modeling memory in VHDL

293