Model Technology Model Sim EE Service Manual

ModelSim EE/SE TutorialVersion 5.3The ModelSim Elite and Special Editions for VHDL, Verilog, and Mixed-HDL Simulation

10 Introduction ModelSim EE/SE TutorialModelSim EE Tutorial PDF online from the ModelSim Help menu in the EE Documentation group, or find ee_tutor.pd

11-100 ModelSim EE/SE TutorialThe List Signal Search dialog box includes these options:You can locate values for the Signal Name: <item_label>

Finding names, and searching for valuesModelSim EE/SE Tutorial 11-101• Search OccurrencesYou can search for the n-th transition or the n-th match o

Finding names, and searching for values11-102 ModelSim EE/SE Tutorial

ModelSim EE/SE Tutorial 12-103Lesson 12 - Using the Wave window The goals for this lesson are:• Practice use of Wave window time cursors.• Practic

Using the Wave window12-104 ModelSim EE/SE TutorialUsing time cursors in the Wave windowWhen the Wave window is first drawn, there is one cursor loc

Using the Wave windowModelSim EE/SE Tutorial 12-105You can also move cursors to the next transition of a signal with these toolbar buttons:Zooming -

Using the Wave window12-106 ModelSim EE/SE Tutorialside of the desired zoom interval, press mouse button 1 and drag to the right. Release when the b

Using the Wave windowModelSim EE/SE Tutorial 12-107Syntax.wave.tree zoomrange f1 f2Argumentsf1 f2Sets the waveform display to zoom from time f1 to f

12-108 ModelSim EE/SE TutorialCombining and grouping items in the Wave windowThe Wave window allows you to combine signals into buses or groups. Use

Using the Wave windowModelSim EE/SE Tutorial 12-109A group is simply a container for any number of signals. It has no value, and the signals contain

ModelSim EE/SE Tutorial Before you begin 11Before you begin Preparation for some of the lessons leaves certain details up to you. You will decide the

12-110 ModelSim EE/SE Tutorial

ModelSim EE/SE Tutorial Index - 111IndexAAssertion errors 33BBatch-mode simulation 41Breakpoints 27continuing simulation after 28CCode Coverage 93cove

112 - Index ModelSim EE/SE Tutorialof a Verilog design 65Home pageModel Technology’s home-page URL 9IInitialization file, see Project filesKKeyboard s

ModelSim EE/SE Tutorial Index - 113applying stimulus to 25display values with examine command 69listing in region 25placing top-level Verilog signals

12 Before you begin ModelSim EE/SE Tutorial Reusing commands from the Main transcriptModelSim’s Main transcript may be saved, and the resulting file

ModelSim EE/SE Tutorial 1-13Lesson 1 - Creating a ProjectThe goals for the first lesson are:• Explore the Welcome to ModelSim dialog box features.•

Creating a Project1-14 ModelSim EE/SE TutorialCreating a ProjectWith the 5.3 release, ModelSim incorporates the file extension .mpf to denote projec

Creating a ProjectModelSim EE/SE Tutorial 1-15Clicking the Create a Project button opens the Create a New Project dialog box and a project creation

Creating a Project1-16 ModelSim EE/SE TutorialNote: A project's .mpf file is always located in the project's directory.6 Once you have spe

Creating a ProjectModelSim EE/SE Tutorial 1-178 Select Options > Edit Project. This opens the Edit Project dialog box.Click the down arrow next t

Creating a Project1-18 ModelSim EE/SE TutorialThe Edit Project dialog also allows you to import a new source file into libraries local to the projec

Creating a ProjectModelSim EE/SE Tutorial 1-19This completes the process of creating a project by copying an existing project. The newly created pro

2ModelSim /VHDL, ModelSim /VLOG, ModelSim /LNL, and ModelSim /PLUS are produced by Model Technology Incorporated. Unauthorized copying, duplication, o

1-20 ModelSim EE/SE Tutorial

ModelSim EE/SE Tutorial 2-21Lesson 2 - Basic VHDL simulation The goals for this lesson are:• Create a library.• Compile a VHDL file.• Start the s

Basic VHDL simulation2-22 ModelSim EE/SE TutorialIn the Create a New Library dialog box select Create: a new library and a logical mapping to it. Ma

Basic VHDL simulationModelSim EE/SE Tutorial 2-23Complete the compilation by selecting counter.vhd from the file list and clicking Compile. Select D

Basic VHDL simulation2-24 ModelSim EE/SE TutorialThe Load Design dialog box allows you to select the library and the top-level design unit to simula

Basic VHDL simulationModelSim EE/SE Tutorial 2-256 Select the entity counter and choose Load to accept these settings.7 Now you can open all of the

Basic VHDL simulation2-26 ModelSim EE/SE TutorialNote how the Run Length selector on the toolbar now indicates 100 (ns is the current default resolu

Basic VHDL simulationModelSim EE/SE Tutorial 2-27The arrow in the Source window points to the next HDL statement to be executed. (If the simulator i

Basic VHDL simulation2-28 ModelSim EE/SE Tutorial14 Select the Continue Run button to resume the run that you interrupted. VSIM will hit the breakpo

Basic VHDL simulationModelSim EE/SE Tutorial 2-29In the Wave window, you can use cursors to:• probe for values - Signal values update whenever you

3Software License AgreementThis is a legal agreement between you, the end user, and Model Technology Incorporated (MTI). By opening the sealed package

Basic VHDL simulation2-30 ModelSim EE/SE Tutorial17 When you’re done experimenting, quit the simulator by entering the command:quit -forceThis comma

ModelSim EE/SE Tutorial 3-31Lesson 3 - Debugging a VHDL design The goals for this lesson are:• Show an example of a VHDL testbench - a VHDL archite

Debugging a VHDL design3-32 ModelSim EE/SE Tutorialvmap work library_2ModelSim modifies the modelsim.ini file for you.5 Start the simulator by selec

Debugging a VHDL designModelSim EE/SE Tutorial 3-339 To add top-level signals to the Wave window, enter the command:add wave *(Signals MENU: View &g

Debugging a VHDL design3-34 ModelSim EE/SE Tutorial12 First, change the simulation assertion options. Make this Main menu selection: Options > Si

Debugging a VHDL designModelSim EE/SE Tutorial 3-3515 From the Main toolbar select the Run button. (Main MENU: Run > Run 1000 ns) (PROMPT: run)No

Debugging a VHDL design3-36 ModelSim EE/SE Tutorial17 Expand the variable named test_patterns by clicking the [+]. (You may need to resize the windo

Debugging a VHDL designModelSim EE/SE Tutorial 3-3721 In the Variables window, expand test_patterns and test_pattern(6) again. Then highlight the .s

Debugging a VHDL design3-38 ModelSim EE/SE Tutorial25Perform these steps on Triggers page in the Modify Display Properties (list) dialog box:• Dese

Debugging a VHDL designModelSim EE/SE Tutorial 3-3927 In the List window select the signal you want to change, then make the property changes in the

4from MTI. All copies of the SOFTWARE, whether provided by MTI or made by you, shall remain the property of MTI or its licensors. You will maintain a

3-40 ModelSim EE/SE Tutorial

ModelSim EE/SE Tutorial 4-41Lesson 4 - Running a batch-mode simulation The goals for this lesson are:• Run a batch-mode VHDL simulation.• Execute

Running a batch-mode simulation4-42 ModelSim EE/SE Tutorial7 To run the batch-mode simulation, enter the following command:vsim -wav saved.wav count

ModelSim EE/SE Tutorial 5-43Lesson 5 - Executing commands at startup The goals for this lesson are:• Specify the design unit to be simulated on the

Executing commands at startup5-44 ModelSim EE/SE TutorialAlso notice that all the windows are open. This is because the view * command is included i

ModelSim EE/SE Tutorial 6-45Lesson 6 - Tcl/Tk and ModelSim This lesson is divided into several Tcl examples intended to give you a sense of Tcl/Tk’s

Tcl/Tk and ModelSim6-46 ModelSim EE/SE TutorialModelSim generates Tcl commands and passes them to the Tcl parser for execution. Commands may be gene

Tcl/Tk and ModelSimModelSim EE/SE Tutorial 6-47The custom-traffic-light interfaceThe subject of our main Tcl/Tk lesson is a simple traffic-light con

Tcl/Tk and ModelSim6-48 ModelSim EE/SE TutorialThe result is a traffic intersection interface similar to this illustration:wm widgetCalls to the ope

Tcl/Tk and ModelSimModelSim EE/SE Tutorial 6-49Tk widgets The intersection illustration points out several Tcl/Tk "widgets". A widget is s

5Limited WarrantyLIMITED WARRANTY. MTI warrants that the SOFTWARE will perform substantially in accordance with the accompanying written materials for

Tcl/Tk and ModelSim6-50 ModelSim EE/SE Tutorialexamples ready-to-run in the tcl_tutorial\solutions directory. Invoke these commands from the ModelSi

Tcl/Tk and ModelSimModelSim EE/SE Tutorial 6-51mouse), or middle (3 button mouse). You can also select a ModelSim or VSIM prompt from the Main trans

Tcl/Tk and ModelSim6-52 ModelSim EE/SE TutorialExample 1 - Create a "hello world" button widget.Before you begin the examples make sure yo

Tcl/Tk and ModelSimModelSim EE/SE Tutorial 6-532 Drag the mouse across the buttons and notice what happens in the Main transcript.Push one of the bu

Tcl/Tk and ModelSim6-54 ModelSim EE/SE Tutorialsource intersection.tcldraw_intersection2 From the ModelSim prompt, use the procedure set_light_state

Tcl/Tk and ModelSimModelSim EE/SE Tutorial 6-55and indicates the next line to be executed. (If the simulator is not evaluating an executable process

Tcl/Tk and ModelSim6-56 ModelSim EE/SE TutorialThe update is accomplished by using a when statement.9 After you have added your North/South widget,

Tcl/Tk and ModelSimModelSim EE/SE Tutorial 6-57(add wave *). You can also change the run length in the Main window. Try using the Run buttons in the

Tcl/Tk and ModelSim6-58 ModelSim EE/SE Tutorial5 Reuse the original commands when you're ready to run the state machine (remember, to copy a pr

ModelSim EE/SE Tutorial 7-59Lesson 7 - Basic Verilog simulation You must be using ModelSim/PLUS or ModelSim/VLOG for this lesson.The goals for this

ModelSim EE/SE Tutorial Table of Contents - 6Table of ContentsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Verilog simulation7-60 ModelSim EE/SE Tutorial4 Before you compile a source file, you’ll need a design library to hold the compilation results

Basic Verilog simulationModelSim EE/SE Tutorial 7-61Note: Remember, a library directory should not be created using UNIX/DOS commands - always use t

Basic Verilog simulation7-62 ModelSim EE/SE TutorialNote: The order in which you compile the two Verilog modules is not important (other than the so

Basic Verilog simulationModelSim EE/SE Tutorial 7-63The Load Design dialog box allows you to select a design unit to simulate from the specified lib

Basic Verilog simulation7-64 ModelSim EE/SE TutorialHDL items can also be copied from one window to another (or within the Wave and List windows) wi

Basic Verilog simulationModelSim EE/SE Tutorial 7-65The Structure window shows the hierarchical structure of the design. By default, only the top le

Basic Verilog simulation7-66 ModelSim EE/SE Tutorial16 Next change the run length to 500 on the Run Length selector and select the Run button again.

Basic Verilog simulationModelSim EE/SE Tutorial 7-67Your Source window won’t look exactly like this illustration because your simulation very likely

Basic Verilog simulation7-68 ModelSim EE/SE TutorialSelect a display radix of Decimal for the signal count. Click OK. This causes the List window ou

Basic Verilog simulationModelSim EE/SE Tutorial 7-6922 Select the Run -all button from the Main toolbar to resume execution of the simulation.(PROMP

ModelSim EE/SE Tutorial Introduction 7IntroductionChapter contentsSoftware versions . . . . . . . . . . .

Basic Verilog simulation7-70 ModelSim EE/SE TutorialThis causes the debugger to step over the function call on line 30. The Step button on the toolb

Basic Verilog simulationModelSim EE/SE Tutorial 7-71When you add a cursor, it is drawn in the middle of the display. Once you have more than one cur

Basic Verilog simulation7-72 ModelSim EE/SE TutorialAnother way to position multiple cursors is to use the mouse in the time box tracks at the botto

ModelSim EE/SE Tutorial 8-73Lesson 8 - Mixed VHDL/Verilog simulationYou must be using ModelSim /PLUS for this lesson.The goals for this lesson are:•

Mixed VHDL/Verilog simulation8-74 ModelSim EE/SE Tutorial3 Let’s create a new library to hold the mixed design. Make this menu selection in the Main

Mixed VHDL/Verilog simulationModelSim EE/SE Tutorial 8-754 Now you can map the new library to the work library. From the Main menu select Design >

Mixed VHDL/Verilog simulation8-76 ModelSim EE/SE TutorialA group of Verilog files can be compiled in any order. Note, however, in a mixed VHDL/Veril

Mixed VHDL/Verilog simulationModelSim EE/SE Tutorial 8-77On the Design tab select the top entity and click Load.8 From the Main menu select View >

Mixed VHDL/Verilog simulation8-78 ModelSim EE/SE TutorialNotice the hierarchical mixture of VHDL and Verilog in the design. VHDL levels are indicate

Mixed VHDL/Verilog simulationModelSim EE/SE Tutorial 8-7913 Now click on the line "s0: cache_set(only)" in the Structure window.The Source

8 Introduction ModelSim EE/SE TutorialModelSim’s graphic interfaceWhile your operating system interface provides the window-management frame, ModelS

Mixed VHDL/Verilog simulation8-80 ModelSim EE/SE TutorialBefore you quit, try experimenting with some of the commands you’ve learned from Lesson 1.

ModelSim EE/SE Tutorial 9-81Lesson 9 - Simulating with Performance Analyzer This lesson introduces the Performance Analyzer and shows you how the ma

Simulating with Performance Analyzer9-82 ModelSim EE/SE Tutorialvcom ringrtl.vhd testring.vhd config_rtl.vhd(MENU: Design > Compile)6 Use the vsi

Simulating with Performance AnalyzerModelSim EE/SE Tutorial 9-83Make a note of the run time of the simulation. (Your run time will depend on the pro

Simulating with Performance Analyzer9-84 ModelSim EE/SE TutorialNotice that the overhead of running the Performance Analyzer is very small (your res

Simulating with Performance AnalyzerModelSim EE/SE Tutorial 9-85Speed up the simulationThe information provided by the Performance Analyzer can be u

Simulating with Performance Analyzer9-86 ModelSim EE/SE Tutorial(MENU: Design > Compile)14 Reset the simulation to time zero and restart with the

Simulating with Performance AnalyzerModelSim EE/SE Tutorial 9-87A lot of time is still being spent in the loops. To further reduce simulation time,

Simulating with Performance Analyzer9-88 ModelSim EE/SE Tutorial20 Run timerun.do again and note the difference in simulation run time. Your simulat

Simulating with Performance AnalyzerModelSim EE/SE Tutorial 9-8922 Set the Under% filter to "2" and click the Update icon. This will filte

ModelSim EE/SE Tutorial Introduction 9We also assume that you have a working knowledge of VHDL and Verilog. Although ModelSim is an excellent tool to

Simulating with Performance Analyzer9-90 ModelSim EE/SE Tutorial23 Take a look at the Ranked Profile view.view_profile_ranked(MENU: View > Other

Simulating with Performance AnalyzerModelSim EE/SE Tutorial 9-9124 Use the report command to output a file with the profile data.profile report -hie

Simulating with Performance Analyzer9-92 ModelSim EE/SE TutorialThis command outputs a hierarchical profile of performance data with the file name h

ModelSim EE/SE Tutorial 10-93Lesson 10 - Simulating with Code Coverage This lesson will introduce ModelSim’s Code Coverage feature, detail the use o

Simulating with Code Coverage10-94 ModelSim EE/SE TutorialThis switch configures the test bench – the ringrtl.vhd file. Changing this entry in the t

Simulating with Code CoverageModelSim EE/SE Tutorial 10-95Note that both testring.vhd and control.vhd are below 90% and, therefore, shown in red in

Simulating with Code Coverage10-96 ModelSim EE/SE Tutorial10 Now, take note of how many times the clocked processes have been executed. Then edit th

Simulating with Code CoverageModelSim EE/SE Tutorial 10-97Note that now both testring.vhd and control.vhd are above 95% and therefore shown is green

Simulating with Code Coverage10-98 ModelSim EE/SE Tutorial16 Compile the lower level blocks with all optimizations switched off. This will cause mor

ModelSim EE/SE Tutorial 11-99Lesson 11 - Finding names, and searching for values The goals for this lesson will be to:• Find items by name in tree